An Architecture of Highly Parallel Computer AP1000

We have developed a highly parallel computer with distributed memory called the AP1000. The system consists of 64 to 1024 processing elements and three independent networks called Torus network (T-net), Broadcast network (B-net), and Synchronization network (S-net). The design goal for the AP1000 is to attain low latency, high throughput communication. To reduce the overall communication latency, we have developed a message controller and a new routing scheme on the T-net. In this paper, we present the design concepts, architecture, and some result from performance test for the AP1000.